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AS3932
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 11. SDI Command Structure
B13
0
0
0
0
B12
0
0
0
0
B11
1
1
1
1
B10
0
0
1
1
B9
1
1
0
0
B8
0
1
0
1
Read/Write register
R10
R11
R12
R13
The last 8 bits are the data that has to be written respectively read. A CS toggle high-low-high terminates the command mode.
If a direct command is sent (B15-B14=11) the bits from B13 to B8 defines the direct command while the last 8 bits are omitted. The Table 12
shows all possible direct commands:
Table 12. List of Direct Commands
COMMAND_MODE
clear_wake
reset_RSSI
trim_osc
clear_false
preset_default
B13
0
0
0
0
0
B12
0
0
0
0
0
B11
0
0
0
0
0
B10
0
0
0
0
1
B9
0
0
1
1
0
B8
0
1
0
1
0
All direct commands are explained below:
-
-
-
-
-
clear_wake: clears the wake state of the chip. In case the chip has woken up (WAKE pin is high) the chip is set back to listening mode
reset_RSSI: resets the RSSI measurement.
trim_osc: starts the trimming procedure of the internal RC oscillator (see Figure 21 )
clear_false: resets the false wake-up register ( R13<7:0> =00)
preset_default: sets all register in the default mode, as shown in Figure 7
Writing of Data to Addressable Registers (WRITE Mode). The SDI is sampled at the falling edge of SCLK (as shown in the following
diagrams).
A CS toggling high-low-high indicates the end of the WRITE command after register has been written. The following example shows a write
command.
Figure 13. Writing of a Single Byte (falling edge sampling)
CS
SCLK
SDI
X
0
0
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
X
Two leading
Zeros indicate
WRITE Mode
www.ams.com/LF-Receiver/AS3932
SCLK rising
edge Data is
transfered from
μC
SCLK
falling edge
Data is
sampled
Revision 1.7
Data is moved
to Address
A5-A0
CS falling
edge signals
end of
WRITE Mode
17 - 34
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